Highly integrated memories with bipolar transistors are known in principle. U.S. Pat. No. 3,815,106, issued June 4, 1974 and assigned to the assignee of the present invention, for instance, describes a monolithic bipolar integrated memory cell, which consists of two cross-coupled flip-flop transistors, two collector load elements, one associated address line connected to the emitters, and one associated bit line pair. The base of each flip-flop transistor is connected to the emitter of an associated complementary address transistor whose collector is linked with the associated bit line and whose base is connected to an address line. The semiconductor structure of a memory cell of this type comprises a first zone of a first conductivity type which forms the emitters of the flip-flop transistors and the bases of the address transistors. A second zone of a second conductivity type is arranged within the first zone and forms the base of one flip-flop transistor as well as the emitter of the associated address transistor. A third zone of the second conductivity type is arranged within the first zone and forms the base of the other flip-flop transistor as well as the emitter of the associated address transistor. A fourth zone of the first conductivity type is arranged within the second zone and forms the collector of one flip-flop transistor. A fifth zone of the first conductivity type is arranged within the third zone and forms the collector of the other flip-flop transistor. Finally, sixth and seventh zones of the second conductivity type are arranged within the first zone and form the respective collector of the address transistors.
In the above MTL memory cell coupling of the read and the switching signals to the bit lines is effected by injection. During reading, part of the injector current is fed across the base region of the NPN transistor to the bit lines and the gate transistors, respectively, whose collector current form the read signal. As a result of this known type of injection coupling, it is possible to produce semiconductor structures permitting a very high packing density of the memory cells in an array. However, the disadvantage of such memory cell structures is that because of the relatively high series resistance of the NPN base region they permit only a relatively low read current. The relatively low read current in turn essentially limits the read speed.
Further, British Pat. No. 1569800 issued Aug. 20, 1980 describes a highly integrated logic circuit with a zone sequence forming an inverting transistor which by an injection region close to the base-emitter junction is supplied with operating current by charge carrier injection and which is controlled at the base. Connected to the injection region is a sense circuit by means of which the conductivity state of the inverting transistor is determined as a function of the current injected back into the injection region when this particular transistor is ON. The inverting transistor is formed by an inversely operated vertical transistor structure with a semiconductor layer arranged on a semiconductor material and forming the emitter zone. This semiconductor layer also comprises the base zone with a collector zone formed therein. Laterally to the base zone, the injection region of the same conductivity type is arranged which is simultaneously used as an emitter for the power supply and as a collector of a lateral transistor for sensing the conductivity state of the inverting transistor.
In the latter case, the bit line injector region is combined with the primary injector, so that the current does not have to flow through the high-resistivity NPN base region. The disadvantage of this circuit is that there is only a very low signal .DELTA.V obtainable between the two line injectors, so that the read speed in connection with a memory or a programmable logic array is adversely affected, i.e., it becomes too low.